System Speedup = 1 / ((1-f) + f/s)
= 1 / (0.75 + 0.25/1.9)
= 1 / (0.75 + 0.13)
= 1.13
6) Addressing Modes
Show how to implement the addressing modes in Figure B.6 using the first three addressing modes.
- Register indirect:
add r4, (r1) add r4, 0(r1)
- Indexed:
add r3, (r1,r2) add r1, r2
add r3, 0(r1)
- Direct:
add r1, (1001) add r1, 1001(r0)
- Memory indirect:
add r1, @(r3) lw r3, 0(r3)
add r1, 0(r3)
- Auto increment:
add r1, (r2)+ add r1, 0(r2)
addi r2, 4
- Auto decrement:
add r1, -(r2) addi r2, -4
add r1, 0(r2)
- Scaled:
add r1, 100(r2)[r3] muli r3, 4
add r2, r3
add r1, 100(r2)
7) ISA Classes
Write code sequences to implement D=(A+B)-(C+D); on the four ISA classes.
- Stack:
push A
push B
add
push C
push D
add
sub
pop D
- Accumulator:
lw A
add B
sub C
sub D
sw D
- Register-Memory:
lw r1, A
add r1, B
sub r1, C
sub r1, D
sw r1, D
- Register-Register:
lw r1, A
lw r2, B
add r1, r2
lw r2, C
sub r1, r2
lw r2, D
sub r1, r2
sw r1, D
8) Five-stage Pipeline
Using pipeline diagrams, find how many cycles are needed to execute the following code sequence.
When stalls are used to solve hazards and branch instructions are resolved in the Execute stage.
When full forwarding paths are used plus stalls (when needed), one branch delay slot, and branch instructions are resolved in the Decode stage.
add r2, r5, r6
lw r1, 0(r2)
sw r1, 4(r2)
beq r4, r4, skip
andi r3, r3, 0
skip: sw r1, 8(r2)
1 1 1 1 1 1 1 1
(a) 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
add r2, r5, r6 F D E M W
lw r1, 0(r2) F D - - E M W
sw r1, 4(r2) F - - D - - E M W
beq r4, r4, skip F - - D E M W
andi r3, r3, 0 F - n n n n
skip: sw r1, 8(r2) F D E M W
Execution takes 15 cycles.
1 1 1 1 1 1 1 1
(a) 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
add r2, r5, r6 F D E M W
lw r1, 0(r2) F D E M W
sw r1, 4(r2) F D E M W
beq r4, r4, skip F D E M W
andi r3, r3, 0 F D E M W
skip: sw r1, 8(r2) F D E M W
Execution takes 10 cycles.
Share with your friends: |
