Department of Computer Science, EBU II, University of California – Riverside, CA, 92521
Education: University of California, Riverside
Ph.D. candidate, Computer Science
Research in Reconfigurable Embedded Systems
University of California, Riverside,
M.S. Computer Science – (2003 – 2005)
Specialization in Real Time Embedded Systems
Application in Low Power Wireless Sensor Systems
GPA 3.65 / 4.0
Indian Institute of Information Technology Allahabad, India (www.iiita.ac.in),
B.Tech in Information Technology – (1999 – 2003)
Intel CTL / STG / PEPL Summer 2006
RFI Mitigation for INTEL Mobile Computing platforms: Algorithm development, test, validation and implementation of a RFI mitigation system to mitigate platform to radio interference.
UC Riverside Computer Architecture and Embedded Systems Group
Graduate Student Researcher, 2005 – 2006.
ROCCC (RIVERSIDE OPTIMIZING COMPILER FOR CONFIGURABLE COMPUTING) support for partial reconfiguration on Virtex-4 FX FPGA. Automatic generation of dynamic co-processors for speeding up software tasks using optimized IP CORE libraries.
Graduate Student Researcher, 2003 – 2005.
RISE (Riverside Sensor) Project comprised of porting the TinyOS from the Atmel AVR architecture to the Chipcon CC1010 (8051). We have interfaced a storage board comprising of SD-CARD and NOR Flash memory on the SPI Bus of the RISE platform. Renesas-M16/C and ARM-7 based co-processing platform are utilized for frequency domain analysis of audio data. Development of a low power time synchronization mechanism based on the WWVB radio signal is underway. Our proposed Sense and Store paradigm which logs data onto low power flash memory built onto the sensor node and involves in-situ data processing has demonstrated typical energy savings of 70% on actual sensor platforms. We are also conducting active research on sensor lifetime maximization based on a given power envelope.
NEC Labs America, Princeton NJ
Research Intern, Summer 2005.
Hardware Assisted RTOS: System level conceptualization and implementation of Hardware assisted Real Time Operating system for Control Dominated Systems. The hardware RTOS includes acceleration for port based communication and shared memory access, and is designed on NEC’s BDL (Behavioral Description Language). The Software runs on an ARM926EJ-S processor that also includes a customized context switching kernel. The complete system is simulated in NEC’s cycle accurate Hardware-Software simulator viz. Classmate and the target application is H263 / MPEG 1 video encoder. Initial speedup gain is about 6.5x vis-à-vis the eCoS and POLIS approaches.
NEC Labs America, Princeton NJ
Research Intern, Summer 2004.
Automatic Softening of SoC Hardware: Development of a patentable idea which involves
(automatic migration of Hardware components to a V850 processor). A cost metric based on silicon gate count vs. performance of various hardware components of an SoC design is used to strategically soften lower performance, but high gate-count tasks from Hardware (ASIC) to Software (V850 processor). We have obtained a 30% gain in silicon floor area, while still meeting the performance requirements of the WEP / WPA encryption test bed.
HFCL R&D Gurgaon, India (Wireless Systems).
Research Intern, January to June 2004.
All digital Software Defined Radio on Xilinx Virtex II FPGA. Simulation in MATLAB and then VHDL implementation using Mentor Graphics FPGA Advantage 5.1, Xilinx ISE 5.2.
The modem was implemented in line with the following papers.
A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications. ”Henry Samueli and Bennett C. Wong”,
A BPSK / QPSK Timing – Error Detector for Sampled Receivers. “Floyd M Gardner”,
A survey of CORDIC algorithms for FPGA based computers. “Ray Andraka”, FPGA 98.
The final system was a digital modem at 20MHz IF, with Automatic Gain Control, Digital Filtering, Timing Recovery, Carrier Recovery and CMA Equalizer.
UC Riverside Library
Systems Administrator: January to March 2004.
Management and Administration of the UC Riverside library’s computing and Information Technology Infrastructure.
Publications in Refereed Conferences:
1. A.Mitra, Z.Guo, A.Banerjee, W.Najjar, “Dynamic Co-Processor Architecture for Software Acceleration on CSoCs”, Internation Conference on Computer Design 2006.
2. A.Banerjee, A.Mitra, M Faloutsos, “Dude – Where’s my Peer”, Globecom 2006.
3. A.Mitra, A.Banerjee, W.Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, “High Performance, Low Power Sensor Platforms Featuring Gigabyte Scale Storage”, SenMetrics MobiQuitous 2005.
4. Z.Guo, A.Mitra, W.Najjar, “AUTOMATION OF IP CORE INTERFACE GENERATION FOR RECONFIGURABLE COMPUTING”, IEEE FPL 2006, Spain.
5. A.Banerjee, A.Mitra, W.Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, “Co-S: A high performance Co-processing Sensor architecture for offloading sensing and data processing”, IEEE SECON 2005.
6. A.Mitra, K Lahiri, M Lajolo, “SOFTENIT: A Methodology for Boosting the Software Content of System-on-Chip Designs”, ACM GLSVLSI 2005. Patents filed in USA and Japan.
7. D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, A. Mitra and W. Najjar, “Towards In-Situ Data Storage in Sensor Databases”, Panhellenic Conference on Informatics, Greece, 2005.
8. A.Mitra, “Bit Error Analysis of New Generation Wireless Transceivers”, IEEE International Conference on Communication Systems 2002, Singapore.
Poster publications in Refereed Conferences:
A.Banerjee, A.Mitra, W.Najjar, “Splitting the Sensor Node”, ACM SenSyS 2005.
S. Neema, A. Mitra, A. Banerjee , W. Najjar, D. Zeinalipour-Yazti, V. Kalogeraki, D. Gunopulos, “NODES: A Novel System Design for Embedded Sensor Systems”, IPSN SPOTS 2005.
Software and Hardware Design of Real Time Embedded Systems.
Developing applications on FPGA viz. VirtexII and Virtex4 FX.
Programming in C, Matlab, VHDL and Assembly.
Computer Architecture, Organization and Design (ARM, MIPS, 80x86)
Wireless Communication and Protocols 802.11a.b.g, TCP / IP.
Intellectual Property Rights esp. Patents. Passed the WIPO distance learning course.
Multilayer Printed Circuit Board design / layout [ Orcad / Cadstar ].
Teaching Assistant: (Fall 2003 - Spring 2006) VHDL, OS, C++ Programming.
1. Offered the Dean’s Fellowship at UC Riverside’s Computer Science Department
2. Founding Member of IIIT Innovation Support Centre, a centre for research in computer hardware projects
3. Moderator of the 1500 member’s strong ‘dspengineering’ group of Yahoo!
4. Gold Medal in Physics, Hyderabad Public School, 12th Grade