Alcapone Power Control



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Alcapone Power Logic.

Description and simulation.


Alcapone Power Control.

The Alcapone Power logic has the control over the power unit in the Alcapone chip.

The Alcapone has three positions in the Endcap, with their own demands.


  1. Ground level.
    SuppOn = ‘1’, The Power Unit also feeds his own logic.
    LVDS inputs selected.

  2. Entering P or N side.
    SuppOn = ‘1’, The Power Unit also feeds his own logic.
    CMOS inputs selected.

  3. On P or N side.
    SuppOn = ‘0’, The Power Unit only feeds the HAL25 chips. The Chip on position 2 feeds his own logic.
    CMOS inputs selected.

The LVDS-CMOS selection has no consequences for the Power Control. The level on the input SuppOn however does interfere with the logic.

When SuppOn is ‘0’ the JTAG logic has control over the Power Supply. If SuppOn is ‘1’ the Power Supply is always switch on.



Stimulus file:

// Verilog stimulus file.

// Please do not create a module in this file.
// Default verilog stimulus.
integer file1;
reg [7:0] count;
`include "AlcaponeTasks.verilog";
// InstEndCapStatus(Reset, TestModeHal, TestModeADC);

// InstIDCode;

// InstBypass;

// InstExTest;

// InstInTest;

// InstSamplePreLoad;

// InstPowerControl(Reset, PowerOn, JTAGOn);

// InstDelayControl(DelayOn, TokenFeedThru);

// InstChipCount(WaitTime, ReadOutTime);

// InstPowerReference(DAC);

// InstADC;

// InstADCInput(ADCIn);

// InstErrorMask(MaskPowerStatus, MaskTokenError, MaskParityError,

// Mask_ErrPside, Mask_ErrNside);

// InstReset;

initial


TCK = 1'b0;

always


#50000 TCK = ~TCK;
initial

Clk = 1'b1;

always

#50000 Clk = ~Clk;


initial


begin

file1 = $fopen("testpower.data");


ADC[7:0] = 8'b00000000;
CMOS_LVDS = 1'b0;

Clk = 1'b0;

FastClear = 1'b0;

PowerStatus = 1'b0;

SupplyOn = 1'b0;

TCK = 1'b0;

TDI = 1'b0;

TDO_BoundaryScan = 1'b0;

TMS = 1'b0;

TRST = 1'b1;

TokenCheck = 1'b0;

TokenIn = 1'b0;

_ErrNside = 1'b1;

_ErrPside = 1'b1;

_POnReset = 1'b1;

count = 8'b00000000;

Action = 4'b0100;
// begin test
#1000 _POnReset = 1'b0;

#199000 _POnReset = 1'b1;


// Default Setup

// Reset = 0 PowerOn = off JTAGOn = off

// PowerStatus = 0
#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = off

// PowerStatus = 0


#100000 count = count + 1;

#500000 InstPowerControl(1'b0, 1'b1, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = off

// PowerStatus = 1


#100000 count = count + 1;

#1000000 PowerStatus = 1'b1;

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = off JTAGOn = off

// PowerStatus = 0


#100000 count = count + 1;

#500000 InstPowerControl(1'b0, 1'b0, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = off JTAGOn = off

// PowerStatus = 0


#100000 count = count + 1;

#1000000 PowerStatus = 1'b0;

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = off

// PowerStatus = 0


#100000 count = count + 1;

#500000 InstPowerControl(1'b0, 1'b1, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = off

// PowerStatus = 1


#100000 count = count + 1;

#1000000 PowerStatus = 1'b1;

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = off

// PowerStatus = 0


#100000 count = count + 1;

#1000000 PowerStatus = 1'b0;

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Mask PowerError
#100000 count = count + 1;

#500000 InstErrorMask(1'b1, 1'b0, 1'b0, 1'b0, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Remove PowerMask
#100000 count = count + 1;

#500000 InstErrorMask(1'b0, 1'b0, 1'b0, 1'b0, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);

// Reset = 1 PowerOn = off JTAGOn = off

// PowerStatus = 0

#100000 count = count + 1;

#500000 InstPowerControl(1'b1, 1'b0, 1'b0);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);

// Reset = 0 PowerOn = on JTAGOn = on

// PowerStatus = 0


#100000 count = count + 1;

#500000 InstPowerControl(1'b0, 1'b1, 1'b1);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// Reset = 0 PowerOn = on JTAGOn = on

// PowerStatus = 1

#100000 count = count + 1;

#1000000 PowerStatus = 1'b1;

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// PowerReference is made b00
#100000 count = count + 1;

#1000000 InstPowerReference(8'b00000000);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);
// PowerReference is made b01010101
#100000 count = count + 1;

#1000000 InstPowerReference(8'b01010101);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);

// PowerReference is made b11111111


#100000 count = count + 1;

#1000000 InstPowerReference(8'b11111111);

#500000 InstEndCapStatus (1'b0, 1'b0, 1'b0);

#1000000 $finish;

#1000000 $fclose(file1);
end

Task File:


task saveEndCapStatus;

begin

$strobe ("save EndCapStatus count = %d", count);



$fstrobe (file1, "EndCapStatus = %b\n\n", EndCapStatus);

$fstrobe (file1, "EndCapStatus count = %d\nPowerOn = %b\nJTAGOn = %b\nPowerStatus = %b\nPowerStatusLatch = %b\nSuppOn = %b\nCMOS_LVDS = %b\nPowerMask = %d\nDelayOn = %b\nTokenFeedThru = %b\nTokenError = %b\nTokenErrorMask = %b\nTestModeHal = %b\nTestModeADC = %b\nDAC = %h\nADC_Input = %b\nWaitTime = %b\nReadOutTime = %b\nErrPside = %b\nErrPsideLatched = %b\nErrPsideMask = %b\nErrNside = %b\nErrNsideLatched = %b\nErrNsideMask = %b\nParityError = %b\nParityErrorLatched = %b\nParityErrorMask = %b\n",count, TestPowerOn, TestJTAGOn, TestPowerStatus, TestPowerStatusLatch, TestSuppOn, TestCMOS_LVDS, TestPowerMask, TestDelayOn, TestTokenFeedThru, TestTokenError, TestTokenErrorMask, TestTestModeHal, TestTestModeADC, TestDac, TestADC_Input, TestWaitTime, TestReadOutTime, Test_ErrPside, Test_ErrPsideLatched, Test_ErrPsideMask, Test_ErrNside, Test_ErrNsideLatched, Test_ErrNsideMask, TestParityError, TestParityErrorLatched, TestParityErrorMask);

end

endtask
task saveDelayControl;



begin

$strobe ("save DelayControl count = %d", count);

$fstrobe (file1, "DelayControl Count = %d\nDelayOn = %b\nTokenFeedThru = %b\n", count, TestDelayOn, TestTokenFeedThru);

end


endtask
task saveChipCount;

begin


$strobe ("save ChipCount count = %d", count);

$fstrobe (file1, "ChipCount Count = %d\nWaitTime = %b\nReadOutTime = %b\n", count, TestWaitTime, TestReadOutTime);

end

endtask
task saveIDCode;



begin

$strobe ("save IDCode count = %d", count);

$fstrobe (file1, "IDCode Count = %d\nIDCode = %d\n", count, TestIDCode);

end


endtask
task savePowerControl;

begin


$strobe ("save PowerControl count = %d", count);

$fstrobe (file1, "PowerControl Count = %d\nPowerOn = %b\nJTAGOn = %b\nPowerStatus = %b\nPowerStatusLatch = %b\nSuppOn = %b\nCMOS_LVDS = %b\nPowerMask = %d\n", count, TestPowerOn, TestJTAGOn, TestPowerStatus, TestPowerStatusLatch, TestSuppOn, TestCMOS_LVDS, TestPowerMask);

end

endtask
task savePowerReference;



begin

$strobe ("save PowerReference count = %d", count);

$fstrobe (file1, "PowerReference Count = %d\nDAC = %d\n", count, TestDac);

end


endtask
task saveADC;

begin


$strobe ("save ADC count = %d", count);

$fstrobe (file1, "ADC Count = %d\nADC = %d\n", count, TestADC);

end

endtask
task saveADC_Input;



begin

$strobe ("save ADC_Input count = %d", count);

$fstrobe (file1, "ADC_Input Count = %d\nADC_Input = %d\n", count, TestADC_Input);

end


endtask
task saveErrorMask;

begin


$strobe ("save ErrorMask count = %d", count);

$fstrobe (file1, "ErrorMask Count = %d\nPowerMask = %d\nTokenErrorMask = %b\nErrPsideMask = %b\nErrNsideMask = %b\nParityErrorMask = %b\n ", count, TestPowerMask, TestTokenErrorMask, Test_ErrPsideMask, Test_ErrNsideMask, TestParityErrorMask );

end

endtask
task IR;



input [3:0] Instruction;

begin


#100000 Action[3:0] = Instruction[3:0];

#500000 TMS = 1'b0;

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b1; //To Select-IR-Scan

#100000 TMS = 1'b0; //To Capture_IR

#100000 TMS = 1'b0; //To Shift-IR

#100000 TDI = Instruction[0];

#100000 TDI = Instruction[1];

#100000 TDI = Instruction[2];

#100000 TDI = Instruction[3];

# 00000 TMS = 1'b1; //To Exit1-IR

#100000 TMS = 1'b1; //To Update-IR

#100000 TMS = 1'b0; //To Run-Test/Idle

end


endtask
task InstEndCapStatus;

input Reset;

input TestModeHal;

input TestModeADC;

// InstEndCapStatus(Reset,TestMode)

begin


//Read Out Endcapstatus
#100000 IR(4'b0100);
#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0 0 1

#100000 TDI = 1'b0; // 0 1 0

#100000 TDI = Reset; // 0 2 PowerOn ResetControl

#100000 TDI = TestModeHal; // 0 3 JTAGOn TestModeHal

#100000 TDI = TestModeADC; // 0 4 PowerStatus TestModeADC

#100000 TDI = 1'b0; // 0 5 PowerStatusLatch

#100000 TDI = 1'b0; // 0 6 Position bit

#100000 TDI = 1'b0; // 0 7 CMOS_LVDS

#100000 TDI = 1'b0; // 0 8 PowerMask

#100000 TDI = 1'b0; // 0 9 DelayOn

#100000 TDI = 1'b0; // 0 10 TokenFeedThru

#100000 TDI = 1'b0; // 0 11 TokenError

#100000 TDI = 1'b0; // 0 12 TokenErrorMask

#100000 TDI = 1'b0; // 0 13 TestModeHal

#100000 TDI = 1'b0; // 0 14 DAC 0

#100000 TDI = 1'b0; // 0 15 DAC 1

#100000 TDI = 1'b0; // 0 16 DAC 2

#100000 TDI = 1'b0; // 0 17 DAC 3

#100000 TDI = 1'b0; // 0 18 DAC 4

#100000 TDI = 1'b0; // 0 19 DAC 5

#100000 TDI = 1'b0; // 0 20 DAC 6

#100000 TDI = 1'b0; // 0 21 DAC 7

#100000 TDI = 1'b0; // 0 22 TestModeADC

#100000 TDI = 1'b0; // 0 23 ADC_Input 0

#100000 TDI = 1'b0; // 0 24 ADC_Input 1

#100000 TDI = 1'b0; // 0 25 ADC_Input 2

#100000 TDI = 1'b0; // 0 26 ADC_Input 3

#100000 TDI = 1'b0; // 0 27 WaitTime 0

#100000 TDI = 1'b0; // 0 28 WaitTime 1

#100000 TDI = 1'b0; // 0 29 WaitTime 2

#100000 TDI = 1'b0; // 0 30 ReadOutTime 0

#100000 TDI = 1'b0; // 0 31 ReadOutTime 1

#100000 TDI = 1'b0; // 0 32 ReadOutTime 2

#100000 TDI = 1'b0; // 0 33 _ErrPside

#100000 TDI = 1'b0; // 0 34 _ErrPsideLatched

#100000 TDI = 1'b0; // 0 35 _ErrPsideMask

#100000 TDI = 1'b0; // 0 36 _ErrNside

#100000 TDI = 1'b0; // 0 37 _ErrNsideLatched

#100000 TDI = 1'b0; // 0 38 _ErrNsideMask

#100000 TDI = 1'b0; // 0 39 ParityError

#100000 TDI = 1'b0; // 0 40 ParityErrorLatched

#100000 TDI = 1'b0; // 0 41 ParityErrorMask

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveEndCapStatus;

end


endtask
task InstIDCode;

begin
// Read Out IDCODE after reset


#100000 IR(4'b0010);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0 1

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 1

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 0

#100000 TDI = 1'b0; // 0 1

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveIDCode;

end

endtask
task InstBypass;



begin

#100000 IR(4'b1111);

end

endtask


task InstExTest;

begin


#100000 IR(4'b0000);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle
end

endtask


task InstInTest;

begin


#100000 IR(4'b0011);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle
end

endtask


task InstSamplePreLoad;

begin


#100000 IR(4'b0001);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle
end

endtask
task InstPowerControl;

input Reset;

input PowerOn;

input JTAGOn;

begin


#100000 IR(4'b0101);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = Reset; // Reset

#100000 TDI = PowerOn; // PowerOn

#100000 TDI = JTAGOn; // JTAGOn

#100000 TDI = 1'b0; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 savePowerControl;

end


endtask

task InstDelayControl;

input DelayOn;

input TokenFeedThru;

begin

#100000 IR(4'b0110);


#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = DelayOn; // 0

#100000 TDI = TokenFeedThru; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveDelayControl;

end

endtask


task InstChipCount;

input [2:0] WaitTime;

input [2:0] ReadOutTime;

begin


#100000 IR(4'b0111);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = WaitTime[0]; // 0

#100000 TDI = WaitTime[1]; // 0

#100000 TDI = WaitTime[2]; // 0

#100000 TDI = ReadOutTime[0]; // 0

#100000 TDI = ReadOutTime[1]; // 0

#100000 TDI = ReadOutTime[2]; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveChipCount;

end

endtask


task InstPowerReference;

input [7:0] DAC;

begin

#100000 IR(4'b1000);


#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = DAC[0]; // 0

#100000 TDI = DAC[1]; // 0

#100000 TDI = DAC[2]; // 0

#100000 TDI = DAC[3]; // 0

#100000 TDI = DAC[4]; // 0

#100000 TDI = DAC[5]; // 0

#100000 TDI = DAC[6]; // 0

#100000 TDI = DAC[7]; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 savePowerReference;

end

endtask


task InstADC;

begin


#100000 IR(4'b1001);
#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveADC;

end

endtask


task InstADCInput;

input [1:0] ADCIn;

begin

#100000 IR(4'b1010);


#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = ADCIn[0]; // 0

#100000 TDI = ADCIn[1]; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveADC_Input;

end

endtask


task InstErrorMask;

input MaskPowerStatus;

input MaskTokenError;

input MaskParityError;

input Mask_ErrPside;

input Mask_ErrNside;

begin

#100000 IR(4'b1011);


#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TDI = 1'b0; // 0

#100000 TDI = 1'b0; // 0

#100000 TDI = MaskPowerStatus; // 0

#100000 TDI = MaskTokenError; // 0

#100000 TDI = MaskParityError; // 0

#100000 TDI = Mask_ErrPside; // 0

#100000 TDI = Mask_ErrPside; // 0

# 00000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle

#100000 saveErrorMask;

end


endtask

task InstReset;

begin

#100000 IR(4'b1100);


#500000 TMS = 1'b0; //To Run-Test/Idle

#100000 TMS = 1'b1; //To Select-DR-Scan

#100000 TMS = 1'b0; //To Capture-DR

#100000 TMS = 1'b0; //To Shift-DR

#100000 TMS = 1'b1; //To Exit1-DR

#100000 TMS = 1'b1; //To Update-DR

#100000 TMS = 1'b0; //To Run-Test/Idle
end

endtask





Timing diagram 1: Power On Reset.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 2: Read the Default state.


PowerOn = 0

JTAGOn = 0

PowerStatus = 0

PowerStatusLatch = 0

SuppOn = 0

CMOS_LVDS = 0

PowerMask = 0


Timing diagram 3: Make PowerOn '1'.


PowerOn = 1 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0



Timing diagram 4: Read EndCapStatus.


PowerOn = 1 JTAGOn = 0 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 5: PowerStatus gets '1', EndCapStatus.


PowerOn = 1

JTAGOn = 0

PowerStatus = 1

PowerStatusLatch = 0

SuppOn = 0

CMOS_LVDS = 0

PowerMask = 0


Timing diagram 6: Make PowerOn '0'.


PowerOn = 0 JTAGOn = 0 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 7: Read EndCapStatus.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 8: PowerStatus gets '0', Read EndCapStatus.


PowerOn = 0

JTAGOn = 0

PowerStatus = 0

PowerStatusLatch = 0

SuppOn = 0

CMOS_LVDS = 0

PowerMask = 0


Timing diagram 9: Make PowerOn '1'.


PowerOn = 1 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 10: Read EndCapStatus.


PowerOn = 1 JTAGOn = 0 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 11: PowerStatus gets '1', Read EndCapStatus.



Timing diagram 12: PowerStatus gets '0', detail.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 1 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 13: Read EndCapStatus.


PowerMask = 0

TokenErrorMask = 0

ErrPsideMask = 0

ErrNsideMask = 0

ParityErrorMask = 0


Timing diagram 14: Set PowerErrorMask.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 1 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 1 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 15: Read EndCapStatus.


PowerMask = 1

TokenErrorMask = 0

ErrPsideMask = 0

ErrNsideMask = 0

ParityErrorMask = 0


Timing diagram 16: Remove PowerErrorMask.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 1 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 17: Read EndCapStatus.


PowerOn = 1

JTAGOn = 0

PowerStatus = 0

PowerStatusLatch = 1

SuppOn = 0

CMOS_LVDS = 0

PowerMask = 0


Timing diagram 18: PowerControl reset.


PowerOn = 0 JTAGOn = 0 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 19: Read EndCapStatus.


PowerOn = 0

JTAGOn = 0

PowerStatus = 0

PowerStatusLatch = 0

SuppOn = 0

CMOS_LVDS = 0

PowerMask = 0


Timing diagram 20: Make PowerOn and JTAGOn '1'.


PowerOn = 1 JTAGOn = 1 PowerStatus = 0

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 21: Read EndCapStatus.


PowerOn = 1 JTAGOn = 1 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 95 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 22: PowerStatus gets '1', Read EndCapStatus.


DAC = h95


Timing diagram 23: Make DAC h00.


PowerOn = 1 JTAGOn = 1 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 00 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 24: Read EndCapStatus.


DAC = 0


Timing diagram 25: Make DAC h55.


PowerOn = 1 JTAGOn = 1 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = 55 ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0

ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 26: Read EndCapStatus.


DAC = 55


Timing diagram 27: Make DAC hff.


PowerOn = 1 JTAGOn = 1 PowerStatus = 1

PowerStatusLatch = 0 SuppOn = 0 CMOS_LVDS = 0

PowerMask = 0 DelayOn = 0 TokenFeedThru = 0

TokenError = 0 TokenErrorMask = 0 TestModeHal = 0

TestModeADC = 0 DAC = ff ADC_Input = 0001

WaitTime = 110 ReadOutTime = 110 ErrPside = 0

ErrPsideLatched = 0 ErrPsideMask = 0 ErrNside = 0

ErrNsideLatched = 0 ErrNsideMask = 0 ParityError = 0



ParityErrorLatched = 0 ParityErrorMask = 0


Timing diagram 28: Raed EndCapStatus.




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